Zero-capacitor random access memory (Z-RAM) cells, also referred to as floating body RAM (FB-RAM) cells, are one-transistor (1T) dynamic RAM cells having floating bodies as charge storages.
FIG. 1 illustrates a structure of a conventional Z-RAM cell 2, which is formed on a buried oxide layer 4. Silicon layer 5 is located on buried oxide layer 4, and shallow trench isolation (STI) regions 6 are formed in silicon layer 5. STI regions 6 encircle a silicon region (including regions 8, 10 and 12), from which Z-RAM cell 2 is formed. Z-RAM cell 2 includes gate electrode 14, gate dielectric 16, source region 8, drain region 10, and floating body 12 between source 8 and drain 10. Due to the isolation by buried oxide layer 4 and STI regions 6, Z-RAM cell 2 is floating.
To write a “1” to Z-RAM cell 2, electrons may be accelerated from source 8 to drain 10 and crash into silicon atoms, creating pairs of electrons and holes. The holes accumulate in floating body 12 and act as the stored bit. To write a “0” to Z-RAM cell 2, the holes may be drawn out through source 8, leaving excess negative charges.
The stored bits may be read by applying a voltage between source region 8 and drain region 10, and measuring the resulting current. For example, a cell storing a “1” passes more current than a Z-RAM cell storing a “0,” hence the state of Z-RAM cell 2 can be determined.
Compared to a conventional dynamic RAM (DRAM) cell, which includes a capacitor for storing a state and a transistor for accessing the capacitor, a Z-RAM cell only includes one transistor, the structure of a Z-RAM cell is thus simpler, and the density of Z-RAM memories may be higher.
The improvements in density and structure, however, are achieved with a price. Currently, Z-RAM memories are formed on silicon-on-insulator (SOI) substrates. SOI substrates, however, cost much more than bulk silicon substrates, the price difference being as high as four times. Accordingly, novel structures and formation methods are needed to reduce the production cost of Z-RAM memories.